This invention is in the field of semiconductor integrated circuits, and is more specifically directed to the formation of buried doped layers in bipolar transistors in such circuits.
Modern bipolar integrated circuits now typically use vertical bipolar transistors as their active elements. These transistors are vertical in the sense that the active base and emitter regions overlie the collector region, with collector-emitter current traveling through the base in substantially a vertical orientation relative to the plane of the surface of the integrated circuit at which the transistor resides. To provide a robust breakdown voltage, the portion of the collector region adjacent the base is relatively lightly doped. This region is often referred to as the “subcollector”. These lightly-doped subcollectors are relatively resistive, however. Therefore, many modern bipolar structures reduce the effective collector resistance by providing a heavily-doped buried collector layer underlying the subcollector. This buried collector layer provides a relatively low resistance path for collector current between the active region of the transistor and a collector contact located away from the base and emitter. Because the collector current need only travel a short distance through the lightly-doped subcollector, before reaching the buried collector layer, the overall collector resistance is minimized, while still providing a high breakdown voltage because of the lightly-doped subcollector.
This construction results in a significant dopant concentration gradient at the interface between the buried collector regions and the much more lightly-doped overlying subcollector. This gradient does not itself present a problem in the stability of the device. However, because this interface must be created relatively early in the manufacturing process, subsequent high temperature processes provide the opportunity for dopant to diffuse from the buried collector region into the more lightly-doped subcollector. A particularly troublesome high temperature process is the epitaxial formation of the subcollector itself, which exposes the wafer to high temperatures for a relatively long period of time. This updiffusion of dopant from the buried collector can cause significant limitations in the performance and precision of modern bipolar circuits.
FIG. 1a illustrates an example of this problem in conventional PNP bipolar transistor 10p. While transistor 10p, in this example, is fabricated in a silicon-over-insulator (SOI) structure, it is to be understood that the issue of diffusion from the buried layer also occurs in a bulk device, although the diffusion deeper into the substrate is harmless. Buried oxide layer 4 is disposed over single-crystal silicon handle wafer 2, and under thin film (single-crystal) silicon layer 6, 6′. This SOI structure may be formed by way of any one of the known conventional techniques, including wafer bonding, implanted oxygen (SIMOX), and the like. Epitaxial layer 8 is disposed over thin film silicon layer 6, and extends toward the surface of the structure as shown. Isolation structures in transistor 10p include deep trench isolation oxide structures 9, and shallow trench isolation structures 12, both of which are formed by etching into (and possibly through) epitaxial layer 8 and thin film silicon layer 6, as desired. The active portions of transistor 10p include the collector region formed in epitaxial layer 8 (i.e., the subcollector), base layer 11, and polycrystalline emitter electrode 15. Emitter contact E, base contacts B and collector contact C make electrical contact to the device by way of a metal contact to tungsten plugs 16e, 16b, 16c, respectively. Diffusion of dopant from emitter electrode 15 into base layer 11 forms the active emitter of the device, at which location the bipolar transistor action takes place.
Buried collector region 6 is a heavily doped (p-type, in this example) portion of thin film silicon layer 6; portions 6′ of this layer away from transistor 10p are relatively lightly doped, or intrinsic silicon. Buried collector region 6 provides a low resistance path between collector contact C and the active collector region. Accordingly, collector-emitter current is conducted vertically through epitaxial layer 8 from buried collector region 6 to emitter 15, as illustrated in FIG. 1a. The provision of buried collector region 6 thus improves the performance of transistor 10p by minimizing series collector resistance.
However, as shown in FIG. 1a, dopant from buried collector region 6 has diffused well into epitaxial layer 8. In FIG. 1a, boundary B illustrates the top surface of thin film silicon layer 6, 6′, from which epitaxial layer 8 was formed. As evident from FIG. 1a, even where epitaxial layer 8 is intrinsic or lightly-doped when formed, boron from buried collector region 6 diffuses by a distance d into epitaxial layer 8, during the high temperature epitaxial process (and during other subsequent high temperature processes). This updiffusion of dopant into epitaxial layer 8 greatly reduces the control of device parameters, as discussed above. Efforts to reduce this updiffusion are known to have detrimental device effects. For example, reduction in the time and temperature of subsequent processes such as densification of isolation structures 9, 12, can reduce the integrity of these oxides. Increasing the thickness of epitaxial layer 8 to compensate for the updiffusion effect not only exacerbates the diffusion itself (by increasing the time or temperature of the process), but also is incompatible with the fabrication of high performance and high-speed devices.
The effect of diffusion from buried collector regions into the device subcollector becomes particularly dramatic in complementary bipolar structures, which by definition include both NPN and PNP bipolar devices, and their respective n-type and p-type buried collector layers. FIG. 1b illustrates the incorporation of transistor 10p into a complementary structure, in which NPN transistor 10n is adjacent to PNP transistor 10p in the same integrated circuit. The construction of transistors 10p, 10n is substantially similar to that illustrated in FIG. 1a for transistor 10p; of course, in the case of transistor 10n, the conductivity type of the doped regions is opposite that of transistor 10p in order for transistor 10n to be of the NPN type.
Typical dopant species for n-type and p-type buried layers 6n, 6p are arsenic and boron, respectively. These species differ in diffusion rate by a factor of ten, however, with boron diffusing much faster than arsenic under equivalent conditions. This difference in diffusion rate is evident from FIG. 1b, in which the subcollector thickness t in PNP transistor 10p is much shorter than the subcollector thickness t in NPN transistor 10n, because boron from p-type buried collector region 6p diffuses much faster than arsenic from n-type buried collector region 6n. Not only does the undesired diffusion from each buried layer reduce the performance of individual transistors 10p, 10n, but the difference in diffusion rate also causes mismatch between the complementary transistors in a given circuit. This mismatch renders the delicate balance of the trade-off between NPN and PNP performance, and the necessary optimization techniques, even more difficult. Besides compromising the ultimate performance of the circuit, this device type asymmetry also can reduce the power efficiency of the complementary design. The trend toward construction of CBiCMOS integrated circuits, which include both complementary bipolar and also complementary metal-oxide-semiconductor (MOS) transistors, will make the effects of buried layer updiffusion even less tolerable.
In addition to the loss of control over the buried layer-subcollector interface, undesired diffusion from heavily-doped buried layers can also contaminate structures away from the buried layers, due to auto-doping during epitaxial growth. An example of such undesired diffusion is illustrated in FIG. 1b, where isolation structure 19 includes dopant from both of buried collector regions 6p, 6n (trench isolation structure 9 being formed after the epitaxial growth of layer 8. Such contamination can result in device leakage, shifts in threshold voltages, and poor breakdown characteristics in bipolar and MOS devices, as well as in diodes and passive devices.
The sensitivity of complementary bipolar devices to differences in diffusion from the n-type and p-type buried layers is conventionally addressed by constraining the thermal budget for subsequent processing, thus limiting the diffusion from these layers and thus limiting the resulting diffusion. These constraints have resulted in very complex processing that is not only costly, but also typically results in the inability to maximize the performance of the NPN and PNP devices in a symmetric manner (i.e., without sacrificing the performance of one for the performance of the other).
Besides impacting device performance, as noted above, diffusion from the buried collector layers also impacts the breakdown voltage of the individual devices. In the complementary bipolar arrangement, in order to optimize symmetric breakdown behavior for the NPN and PNP devices, the significant difference in diffusion rates necessitates a trade-off between device breakdown for one of the transistor types (PNP) and collector resistance of the other of the transistor types (NPN). In addition, the asymmetric diffusion of the dopant species also creates mismatching of the device characteristics of NPN and PNP devices in a complementary circuit; such mismatches are especially undesirable, considering that the matching of device characteristics is a primary reason for realizing a circuit in complementary bipolar technology in the first place. In addition, the tight constraint on thermal budget because of the rapid diffusion of boron from the buried collectors of the PNP devices also increases the likelihood of mismatch among the PNP devices themselves, as these devices can become quite sensitive to the processing conditions that fall within the thermal budget constraints. These and other device sensitivities are also exacerbated as the physical device sizes continue to scale toward ever decreasing dimensions.